1. Field of Invention
Embodiments of the present invention relates to a method of manufacturing a split gate type nonvolatile memory device in which a control gate is formed using a self aligning method.
This application claims the priority of Korean Patent Application No. 03-77765 filed on Nov. 4, 2003 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
Nonvolatile memory devices have become increasingly popular in various fields (e.g. mobile communications and memory card technologies). In nonvolatile memory devices, data can be electrically erased and recorded, while being retained without a power supply. A transistor included in a nonvolatile memory device may be a stacked gate transistor that includes a floating gate, an insulating film, and a control gate (which are sequentially stacked) or a split gate transistor (incorporating a split gate structure).
FIG. 1 is a cross-sectional view of a nonvolatile memory device with a split gate transistor. The split gate type memory device of FIG. 1 includes a source region 15 (formed in a predetermined region on a substrate 10) and a pair of floating gates 20 (formed adjacent to the both ends of the source region 15 on the substrate 10). Upper faces of the floating gates 20 are covered by intergate oxide films 25. Side walls of the floating gates 20 (opposite to the source region 15) are covered by control gates 30. The control gates 30 cover upper faces of the intergate oxide film 25 in one direction and cover a portion of the substrate 10 on an opposite side of the source region 15 of the floating gate 20 in the other direction. Drain regions 35 are formed on the substrate 10 adjacent to the control gate 30. The drain regions 35 partially overlap the control gate 30. A gate insulating film 40 is formed between the floating gate 20 and the substrate 10. The gate insulating film 40 extends underneath the floating gate 20. A tunnel insulating film 45. The tunnel insulating film 45 is under the control gate 30.
In a split gate type memory device, floating gates 20 and control gates 30 have a split configuration. The data can be stored by electron injection (writing) and discharge (erasing) to and from the floating gate 20, by varying currents. In a writing mode, when applying a high voltage (e.g. 15 V) to the source region 15 and applying an appropriate voltage to the drain region 35, hot electrons are injected into the floating gate 20. The hot electrons pass through the gate insulating film 40 from the substrate 10 under the floating gate 20 adjacent to the control gate 30. The gate insulating film 40 may increase electrical potential of the floating gate 20 by coupling the voltage applied to the source region 15. In an erasing mode, a high electric field (on an edge tip of the floating gate 20) is generated when more than 15 V is applied to the control gate 30. Electrons in the floating gate 20 are then discharged to the control gate 30. The intergate oxide film 25 maintains a large electric potential difference between the control gate 30 and the floating gate 20 by reducing the coupling ratio between the two gates 20 and 30. The electron injection into the floating gate 20 is accomplished by a Channel Hot Electron Injection (CHEI) method. The electron discharge is accomplished by a Fowler-Nordheim (F-N) tunneling through the tunnel insulating film 45 interposed between the floating gate 20 and the control gate 30.
The split gate type memory device of FIG. 1 may be manufactured as follows. First, a gate insulating film 40 is formed on the entire surface of a semiconductor substrate 10. Next, a first polysilicon film (for forming a floating gate 20 with a predetermined thickness) is formed on the gate insulating film 40. After patterning the first polysilicon film (by using a photolithography process), the first polysilicon film is thermally oxidized, forming the floating gate 20 and the intergate oxide film 25 covering the floating gate 20. An insulating film is formed by CVD on the entire surface of the substrate 10 on which the intergate oxide film 25 is formed. A tunneling insulating film 45 is then formed by patterning the insulating film by using a photolithography process, as depicted in FIG. 1. A control gates 30 is formed of polysilicon by patterning (using a photolithography process) a second polysilicon film. The second polysilicon film is formed by conformally depositing polysilicon on a substrate 10 on which the tunneling insulating film 45 is formed.
In a method of manufacturing a split gate type memory device, a photolithography process is utilized for forming control gates 30. However, there is high probability of photo misalignment in the photolithography process that can cause variation in channel length overlapping. If there is any misalignment, an effective channel length of the control gate varies from one cell to another, resulting in characteristic differences between the two cells which are in a mirror image. For example, an Odd cell (effective length: L1) and an Even cell (effective length: L2) may not be equal. The variation in effective channel length of the control gate 30 causes the variation in threshold voltages of the cells. The variation of threshold voltages of the odd cell and the even cell causes difference in on-current characteristics of the cells, that reduce uniformity of the cells.